Embedded Systems World

In most processors, the ALU (Arithmetic Logic Unit) operates only on CPU registers, not directly on memory. Example: Asm LDR R1, [R0] ADD R2, R1, R3 STR R2, [R0] The CPU first loads data from memory into registers, performs the operation, and then stores the result back. But why? 📌 Speed Registers are inside the CPU core, so ALU operations can often complete in a single clock cycle. 📌 Memory is slower Accessing RAM involves the address bus, memory controller, and data bus, which takes many cycles. 📌 Simpler CPU design Keeping ALU operations on registers allows faster pipelines and predictable instruction timing. 💡 Key Insight Efficient firmware minimizes memory access and performs as many operations as possible in registers. That’s why optimized drivers often read a register once, modify it in CPU registers, and write it back. #EmbeddedSystems #Firmware #ComputerArchitecture #Microcontrollers #EmbeddedLearning #WhySeries

In most microcontrollers, peripherals like GPIO, UART, SPI, and Timers are accessed as if they were normal memory locations. Example: C GPIO->OUT |= LED1; Behind the scenes, the CPU is simply reading or writing a specific memory address assigned to that register. Example memory map: 0x00000000 → Flash   0x20000000 → SRAM   0x40000000 → Peripherals So when firmware accesses: 0x40020014 the CPU is actually talking to a GPIO register, not RAM. Why this design? ✔ Simplifies CPU design — same instructions for memory and peripherals ✔ Allows standard load/store instructions to control hardware ✔ Makes firmware development easier ✔ Enables compilers to generate simple and efficient code 💡 Key insight Peripherals are not accessed with special instructions. They are simply memory addresses mapped to hardware registers. That’s why embedded firmware often looks like: Memory → Register → Processing → Memory #EmbeddedSystems #Firmware #Microcontrollers #EmbeddedLearning ...

When learning assembly or reading compiler output, you will often see instructions like: ADD R0, R1, R2 or LDR R1, [R0] Notice something interesting: Most operations happen between registers, not directly on memory. Why is this the case? The Reason: Speed Registers are located inside the CPU itself. Memory (RAM or Flash) is outside the CPU core and accessed through buses. Because of this, memory access takes significantly longer than register access. Typical comparison: Storage Location Access Speed Register ~1 CPU cycle SRAM multiple cycles Flash even more cycles So if the CPU had to access memory for every operation, programs would run much slower. Example Consider this simple C code: x = a + b; Conceptually, the CPU performs something like: LDR R1, [a] LDR R2, [b] ADD R0, R1, R2 STR R0, [x] The values are first loaded into registers, then the arithmetic operation is performed. Why CPUs Prefer Registers Registers allow the processor to: • execute operations faster • reduce memory acc...

In assembly, you often see instructions like: ADD R0, R0, #5 Here #5 is embedded directly inside the instruction. This is called Immediate Addressing. But what happens if we write the following C code? x = x + 100000; Instead of placing the value directly inside the instruction, the CPU may generate something like: LDR R1, =100000 ADD R0, R0, R1 Why can’t the processor simply execute: ADD R0, R0, #100000 The Reason: Instruction Size Is Limited Most ARM instructions are 32 bits wide. Those 32 bits must encode several pieces of information: the operation (ADD, SUB, MOV, etc.) the destination register the source register the immediate value Conceptually, the instruction looks like this: [ opcode | registers | immediate value ] Since the instruction must store multiple fields, only a limited number of bits remain for the constant. As a result, very large numbers cannot always fit directly inside the instruction. What Happens When the Constant Is Too Large? When the constant cannot be encod...

This behavior simplifies PC-relative addressing. Example instruction: LDR R0, [PC, #0] If the instruction is at: 0x1000 PC already contains: 0x1008 So data is loaded from 0x1008. This is commonly used for literal pools and constant loading. The Key Insight The PC does not point to the instruction currently executing. It points to the instruction already fetched ahead in the pipeline. In ARM state: PC = Current Instruction Address + 8 because the processor pipeline has already fetched future instructions. #EmbeddedSystems #ARM #Firmware #Microcontrollers #EmbeddedLearning #ComputerArchitecture